Modulators for wireless transmission schemes such as EDGE or WCDMA, in which part or all of the information is carried in the signal amplitude, need to be linear. Non-linearity causes transmission in frequencies outside the intended channel, causing interference in neighbouring channels. These problems are acute in modulators providing relatively high power outputs, where large signal currents cannot be switched instantaneously.
A typical double-balanced mixer 1, commonly used in a linear modulator, is shown in FIG. 1. A pair of nodes 2 and 3 is provided as an input for a differential modulating signal. The latter is marked as voltage Vi and −Vi being applied to 2 and 3, respectively. Another pair of nodes 7 and 8 is provided as an input for a local oscillator signal. In the remainder of the text we will refer to the local oscillator signal actually applied to nodes 7 and 8 as the clock signal. This facilitates the description of the various versions of the local oscillator signal typically found in a modulator, such as the signals generated by the local oscillator or synthesizer (the LO signal), its phase shifted and possibly frequency-divided versions, and the final in-phase (I) and quadrature (Q) switching signals at the radio carrier frequency that actually open and close the commutating switches in a double balanced mixer. The output of the double-balanced mixer is also in differential form and is provided by nodes 10 and 11. A first pair of transistors M1 and M2, having their source terminals connected to node 4, gate terminals respectively connected to 2 and 3, and drain terminals respectively connected to nodes 5 and 6, form a transconductor to convert the differential signal Vi into a differential current signal i. In FIG. 1 the said differential current signal is marked together with the bias current IB (connected between node 4 and ground) as IB/2+i for node 5 and IB/2−i for node 6. A second pair of NMOS transistors M3 and M4 have their sources connected to node 5 and their drains respectively connected to outputs 10 and 11. A third pair of NMOS transistors M5 and M6 have their sources connected to node 6 and their drains respectively connected to outputs 10 and 11. A pair of clock signals LO+ and LO− in antiphase is provided by a local oscillator 9 (or clock generator 9 if it receives the local oscillator signal and generates the clocking signals with appropriate phasing and delays). These are applied respectively to input nodes 7 and 8 of the double balanced mixer and used to open and close its switches, which are typically provided as MOSFET or BJT transistors and shown here as M3, M4, M5 and M6. Clock signal LO+ at node 7 is connected to the gates of transistors M3 and M6, while clock signal LO+ at node 8 is connected to the gates of transistors M4 and M5. Since the clocks are in anti-phase transistors M3 and M6 are generally on while transistors M4 and M5 are off, in which state node 5 is connected to output node 10 via M3 and node 6 is connected to output node 11 via M6, and vice versa, in which state node 5 is connected to node 11 via M4 and node 6 is connected to node 10 via M5.
Ideally the transitions between the said two states should be instantaneous, so that mathematically the four commutating switches M3, M4, M5 and M6, referred to as the mixer core, serve to realize a multiplication of the input current i by an alternating sequence of 1s and −1s at the frequency of the clock signal. In practical implementations, however, the transition time τ between the two states is non-zero and depends both on the dimensions of the switches and the magnitude of the current being switched. During the transition all four transistors M3, M4, M5 and M6 are on and harmonics of the signal current i are created in the output. With dimensions of the switching transistors limited by speed and noise considerations in a particular application, increasing magnitude of the signal current will result in increasing transition time τ, and consequently nonlinearity of the mixer core.